Xelec hardware engineering
Firmware, boards, sensors and connected devices — engineered for production, not the demo table.
Capability
Most programmes lose months in handovers. We hold the whole chain, so trade-offs get made once.
Figures on this page are illustrative placeholders pending verified capability data.
Eight services
Each engagement is scoped to a physical deliverable.
H-01
A connected product that works on the bench and falls over as a fleet.
Device, gateway, connectivity and telemetry — with provisioning, identity and secure OTA designed in from the start.
Deliverables
H-02
You need proof the thing can exist before anyone will fund it.
Dev-kit bring-up to first custom PCB, plus an honest read on power, thermal, size and volume cost.
Deliverables
H-03
Firmware written once, then nobody can safely change it.
Bare-metal and RTOS firmware, drivers, secure boot and signed OTA — with a hardware-in-the-loop test rig.
Deliverables
H-04
A prototype no contract manufacturer will quote against.
Schematics, PCB layout, signal and power integrity, enclosure coordination, DFM and certification preparation.
Deliverables
H-05
The model gets blamed when the capture was wrong all along.
Optics, lighting, sampling and synchronisation specified with the model, then validated on target silicon — Jetson-class modules included.
Deliverables
H-06
A vision model that only ever ran on a workstation GPU.
Jetson Orin Nano and Jetson-class deployments: model optimisation and quantisation, carrier board, thermals, camera pipeline, fleet OTA.
Deliverables
H-07
Decisions about a site made from spreadsheets and memory.
Sensors and cameras instrument the real space, feeds fuse into a live model of it, then you simulate changes before you make them.
Deliverables
H-08
A shipped device with no one left who understands it.
Board revisions, obsolescence and second-source swaps, firmware maintenance, field diagnostics and fleet health.
Deliverables
How an engagement runs
Stop at any stage and keep the artefacts.
01
Constraints first: duty cycle, power, environment, certification target, volume and landed cost.
1–2 weeks
02
First board and firmware skeleton — a working unit that proves the risky part.
4–8 weeks
03
Layout hardening, DFM review, thermal and power validation, test fixtures, certification prep.
6–12 weeks
04
A small run in real conditions, instrumented, with OTA and diagnostics already live.
4–8 weeks
05
Transfer to manufacturing, then revisions, sourcing changes and fleet operation under an SLA.
Ongoing
Why both under one roof
An AI company sends a cloud API. A design house sends a board. Neither owns the trade-off.
Capture designed for the model
Sensor choice, optics and sampling specified against the accuracy target.
Compute sized to the workload
Silicon selected after the distilled model is profiled — no accelerator you never saturate.
Data that never leaves the site
Inference at the station keeps imagery, audio and documents on your network.
One accountable team
No argument about whether it is the model, the firmware or the sensor.
Next step
Cycle time, power budget, certification target, landed cost — we will tell you the size of the programme.